In recent years, a CMOS image sensor has been widely used for a digital camera, a digital camcorder, a camera unit for a portable telephone, and the like. Owing to the requirements of the reduction of the number of parts, the reduction of power consumption, and the like, a CMOS image sensor incorporating A/D conversion circuits has been researched. As a format of the CMOS image sensor, there is a format called a column A/D providing an A/D conversion circuit to each column of a pixel arrangement. Various A/D conversion formats have been proposed to be used for the column A/D, and among them integration type A/D conversion formats disclosed in Japanese Patent Application Laid-Open Publications No. 2002-232291 and No. 2005-348325 are known. If conversions are performed in two stages of higher order bits and lower order bits like the integration type A/D converter disclosed in Japanese Patent Application Laid-Open No. 2002-232291, then the conversion time becomes proportional to 2×2N/2, and the method has a feature capable of shortening the conversion time in comparison with, for example, the format of comparing an input signal with a triangular wave.
The A/D conversion format disclosed in Japanese Patent Application Laid-Open No. 2005-348325 performs an A/D conversion by holding a signal from a pixel in a storage unit, followed by charging and discharging by a fixed signal. Since the A/D conversion format disclosed in Japanese Patent Application Laid-Open No. 2005-348325 also performs an A/D conversion in two stages of the higher order bits and the lower order bits, the A/D conversion format can shorten the time necessary for the A/D conversion in comparison with that of the conversion format of comparing an input signal with a triangular wave.
However, following problem occurs when the A/D converter disclosed in Japanese Patent Application Laid-Open No. 2002-232291 is used as a column A/D. If there is a discrepancy in a ratio of a changing quantity of an electric charge held in a capacitor per clock for a higher order bit conversion (unit integration quantity for the higher order bit conversion) to a changing quantity of an electric charge held in the capacitor per clock for a lower order bit conversion (unit integration quantity for the lower order bit conversion), a differential linear error is caused. For example, if 12 bits A/D conversion is performed in stages of higher order digits of 6 bits and lower order digits of 6 bits, the unit integration quantity for the higher order bit conversion is ideally required to be 64 times as large as the unit integration quantity for the lower order bit conversion, but an error is caused owing to the relative accuracy of the elements constituting the circuit and the like in the actual circuit. The relative accuracy of the elements is affected by, for example, dispersion that occurs when manufacturing the elements.
FIG. 8 cites FIG. 5 of Japanese Patent Application Laid-Open No. 2002-232291. Some of the reference numerals are deleted for simplification. The A/D converter illustrated in FIG. 8 amplifies a signal Vc1, which is a signal changing in a staircase wave, at the gain of C5/C4 for the higher order bit conversion, and on the other hand amplifies a signal Vc2, which has the same gradient as that of the signal Vc1 and the reverse polarity to that of the signal Vc1, at the gain of C6/C4 for the lower order bit conversion. The unit integration quantity for higher order bit conversion is C5/C6 times as large as the unit integration quantity for the lower order bit conversion. However, since the capacitor elements C5 and C6 are ones being different at each column, the relative accuracy of the capacitor elements C5 and C6 is different in each column. Thereby, it is conceivable that the value C5/C6 is slightly different at each column. In particular, if the column widths of a pixel arrangement are reduced in association with the reduction of pixel sizes, then the sizes of the capacitor elements able to implement within the columns, that is, capacitor values, become smaller, and consequently the relative accuracy of the capacitor elements generally become worse. If the error of the ratio of the unit integration quantity for the higher order bit conversion to the unit integration quantity for the lower order bit conversion between columns becomes nonnegligible to the required accuracy of linearity, the necessity of storing a correction coefficient into each column and executing correction operations arises. This causes the problem in which linearity correction processing becomes a very large load especially in the case where the number of conversion bits increase.
On the other hand, FIG. 9 is a citation of FIG. 6 of Japanese Patent Application Laid-Open No. 2005-348325. Reference numerals are newly added for the sake of a description. In the configuration of FIG. 9, a current based on the potential difference between a fixed voltage V_DE1 or V_DE2 and the electric potential at the inverting input terminal (−) of an operational amplifier Amp, and the magnitude of a resistance R flows through the resistance R. The electric potential at the inverting input terminal of the operational amplifier Amp ideally becomes equal to the electric potential at the non-inverting input terminal (+) thereof owing to the imaginary ground thereof. However, in an actual circuit, the two input terminals of the operational amplifier Amp have different electric potential since the characteristics of the elements constituting the operational amplifier Amp are not necessarily ideal. Therefore, the difference appears as an offset. That is, the ideal integration is not performed due to the offset caused by the elements constituting the operational amplifier Amp.
If the resolution of an A/D converter is not high, the discrepancy of the ratio from its ideal value does not affect significantly. However, if the resolution becomes higher, the discrepancy from the ideal value becomes nonnegligible, and the problem that the accurate A/D conversion results cannot be obtained is caused.